Non-volatile memory (NVM) cells, such as split gate NVM cells, have achieved widespread adoptions for code and data storage applications. A split gate NVM cell may include an access gate (AG) and a floating gate (FG) disposed on a substrate. An AG is disposed adjacent to a FG separated by a tunneling dielectric layer. Both the AG and FG are separated from the substrate by an AG dielectric and a FG dielectric. Below the gates is a channel of the memory cell. The gates are separated from each other by an intergate dielectric. The AG serves as a wordline (WL).
Memory operations, such as programming and erasing, may involve, for example, charging or discharging electrons from a floating gate (FG) of the split gate NVM cell. The charging and discharging of electrons may be achieved by hot carrier injection (HCI) or Fowler Nordheim (FN) tunneling. An important aspect of split gate NVM cells is their performance, which includes efficient programming.
However, conventional split-gate NVM cells may suffer from inefficient programming efficiency. For example, a conventional split-gate NVM cell may be subjected to an increased electric field at the wordline (WL) corner. The increased electric field causes unnecessary HCI to the WL. This reduces hot electron injection to the FG. As a result, the programming efficiency is reduced.
From the foregoing discussion, it is desirable to provide a split-gate NVM cell with improved programming efficiency.